Solutions for a single carrier 40 Gbit/s downstream long-reach passive optical network

This paper presents a single carrier 40 Gbit/s downstream long-reach passive optical network (LR-PON) topology as candidate for upgrading cur rent f ber infrastructure towards higher data rates. A 100 km LR-PON network was investigated and 2 solutions to overcome chromatic dispersion were proposed. Firstly, a dispersion compensated element is added to compensate the mean length of the feeder f ber. Secondly, an advanced modulation scheme, i.e. 3-level electrical duo-binary is introduced. This scheme has the advantage of allowing lower bandwidth APDs and requires only limited additional electronics. Furthermore, to overcome the inherent discrepancy between aggregated line rate and user rate, and hence the reduced power effciency, the BiPON protocol is added to minimize signal processing at the high line rates

Fast H.264 intra prediction for network video processing

This letter proposes a fast parallel and deeply pipelined architecture for realtime H. 264 intra 4x4 prediction capable of handling up to 32 High Definition video streams (1920x1080 @ 30 fps) simultaneously, while offering high flexibility and consuming only a fraction of resources available on modern FPGA's. The design has been validated on target using a state of the art Altera Stratix IV FPGA

Influence of jitter on limit cycles in bang-bang clock and data recovery circuits

In bang-bang (BB) clock and data recovery circuits (CDR) limit cycles can occur, but these limit cycles are undesired for a good operation of the BB-CDR. Surprisingly, however, a little bit of noise in the system is beneficial, because it will quench the limit cycles. Until now, authors have always assumed that there is enough noise in a BB-CDR such that no limit cycle occurs. In this work, a pseudo-linear analysis based on describing functions is used to investigate this. In particular, the relationship between the input noise and the amplitude of eventual limit cycles is investigated. An important result of the theory is that it allows to quantify the influence of the different loop parameters on the minimal amount of input jitter needed to destroy the limit cycle. Additionally, for the case that there is not enough noise, the worst case amplitude of the limit cycle (which is unavoidable in this case) is quantified as well. The presented analysis exhibits excellent matching with time domain simulations and leads to very simple analytical expressions

Voltage controlled oscillators for 40Gbit/s cascaded bit-interleaving PON

Technologies such as the Internet-of-Things and cloud services demand dynamic bandwidth allocation flexibility, which is not offered by the currently deployed solutions. The Bit-Interleaving PON (BiPON) and its cascaded extension the Cascaded Bit-Interleaving PON (CBI-PON) offer a solution that allows to increase bandwidths, reduce power consumption and have a much more flexible dynamic bandwidth allocation scheme. CBI-PON consists of multiple levels of BiPON with different line rates. For each of these line rates, clock-and-data recovery must be performed, which requires a set of different Voltage Controlled Oscillators (VCOs). This paper presents the VCOs designed for the CABINET chip, an implementation of a CBI-PON network device, allowing clock-and-data recovery for 40Gbit/s, 10 Gbit/s and 2.5 Gbit/s line rates

Fast determination of instability in a nonlinear Clock and Data Recovery circuit

C

A low power 40 Gbit/s cascaded extension to bit-interleaving optical networks enabling next-generation metro/access connectivity

C

The 40 Gbps cascaded bit-interleaving PON

A

Fast synchronization 3R burst-mode receivers for passive optical networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed

Performance evaluation of single carrier 40-Gbit/s downstream for long-reach passive optical network

This paper presents a new long reach PON (LR-PON) scenario operating at a single carrier of 40-Gbit/s for downstream, as an upgrade option of the LR-PON evolutionary strategy. An electrical 3-level duobinary modulation format was proposed for the 40-Gbit/s downstream transmission. In this paper the required optical signal to noise ratio (OSNR) and optical power budget were investigated based on analytic calculation of OSNR requirements and cascaded analysis with an optical link model. Numerical simulation results show that the 40-Gbit/s downstream operating at the wavelength of 1.5 μm can support a long reach up to 100 km and a high split ratio up to 256